1 ps9009a 04/03/09 redriver is a trademark of pericom semiconductor. features ? sata2 i, m ; external sata2 ? two 3.0gbps differential signal pairs ? adjustable receiver equalization ? 100-ohm differential cml i/o?s ? independent analog output swing adjustment ? independent analog output emphasis control ? input signal level detect and squelch for each channel ? oob support ? low power (200mw per channel) ? stand-by mode ? power down state ? v dd operating range: 3.3v ? packaging: ? 20-tqfn (3.5x 4.5mm, zh) ? 20-tqfn (4x 4mm, zd) description pericom semiconductor?s PI3EQX3851B is a low power, signal redriver. the device provides programmable equalization, to optimize performance over a variety of physical mediums by reducing inter-symbol interference. PI3EQX3851B supports two 100-ohm differential cml data i/o?s between the protocol asic to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user?s platform. the integrated equalization circuitry provides exibility with signal integrity of the signal before the redriver. a low-level input signal detection and output squelch function is provided for each channel. each channel operates fully independently. when the channels are enabled (ce=1) and operating, that channels input signal level (on xi+/-) determines whether the output is active. if the input signal level of the channel falls below the active threshold level (vth-) then the outputs are driven to the common mode voltage. in addition to signal conditioning, when ce = 0, the device enters a low power standby mode. block diagram PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment pin diagram (top side view) 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 10 11 120 a_eq dnc ai+ ai- vdd33 bo- bo+ b_em a_em ao+ ao- vdd33 dnc bi- bi+ b_eq b_os ce gnd a_os gnd xi + cml cml limiting amp equalizer signal detection power management - repeated 2 times - xi ? xo + xo ? ce x_eq x_em x_os 19 1 2 3 4 5 7 16 15 14 13 12 11 10 8 9 18 17 a_eq1 vdd33 ai+ ai- bo- bo+ b_em a_em ao+ ao- vdd33 bi- bi+ b_eq0 b_os ce gnd a_os gnd 6 b_eq1 20 a_eq0 3.5x4.5mm (zh) 4x4mm (zd) 08-0252
2 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. pin description zd pin # zh pin # pin name type description 16 19 a_em input output emphasis adjustment for channel a. connects to resistor (tied to ground) to allow ne adjustment of emphasis level. (see output adjustment table.) 20 19 2 - a_eq0 a_eq1 input selection pin(s) for equalizer of ai, see input equalizer adjustment table. with internal 50k-ohm pull-up resistor. 17 20 a_os input output swing adjustment for channel a. connects to resistor (tied to ground) to allow ne adjustment of output swing level. (see output swing adjustment table.) 1 2 3 4 ai+ ai- input cml input forward channel a. with internal 50-ohm pull up, connected to inter- nal bias voltage. 15 14 18 17 ao+ ao- output cml output channel a. with internal 50-ohm pull up, connected to internal bias voltage. 6 9 b_em input output emphasis adjustment for channel b. connects to resistor (tied to ground) to allow ne adjustment of emphasis level. (see output adjustment table.) 10 9 12 - b_eq0 b_eq1 input selection pin(s) for equalizer of bi. see input equalizer adjustment table. with internal 50k-ohm pull-up resistor. 7 10 b_os input output swing adjustment for channel b. connects to resistor (tied to ground) to allow ne adjustment of output swing level. (see output adjustment table.) 11 12 13 14 bi+ bi- input cml input return channel b. with internal 50-ohm pull up, connected to internal bias voltage. 5 4 8 7 bo+ bo- output positive cml output channel b. with internal 50-ohm pull up, connected to internal bias voltage. 8 11 ce input chip enable "high" provides normal operation. "low" for power down mode. with internal 50k-ohm pull-up resistor. 18, cen- ter pad 1, center pad gnd gnd supply ground. 3, 13 6, 16 vdd33 power 3.3v supply voltage 10%. place 100nf and 1nf bypass capacitors to ground, as close to the device as possible. - 5, 15 dnc - do not connect input equalizer adjustment (zh) x_eq compliance channel @ 1.5 ghz 0 3.5db 1.0db 1 7.5db 1.0db input equalizer adjustment (zd) x_eq1 x_eq0 compliance channel @ 1.5 ghz 0 0 3.5db 1.0db 0 1 4.5db 1.0db 1 0 6.5db 1.0db 1 1 7.5db 1.0db 08-0252
3 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. output adjustment swing pre-emph 0db (mv) pre-emph 0db (mv) pre-emph 0db (mv) pre-emph 0db (mv) pre-emph 0db (mv) pre-emph 0db (mv) pre-emph 0db (mv) pre-emph 0db (mv) db k-ohm k-ohm k-ohm k-ohm k-ohm k-ohm k-ohm k-ohm k-ohm ?0.5 500 500 561 595 630 667 749 840 942 0 530 530 595 630 667 749 840 942 1057 0.5 561 561 630 667 749 840 942 1057 1187 1 595 595 667 749 840 942 1057 1187 1331 2 667 667 749 840 942 1057 1187 1331 3 749 749 840 942 1057 1187 1331 4 840 840 942 1057 1187 1331 5 942 942 1057 1187 1331 6 1057 1057 1187 1331 7 1187 1187 1331 8 1331 1331 08-0252
4 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. storage temperature ........................................................ ?65c to +150c supply voltage to ground potential ................................... ?0.5v to +4.6v dc sig voltage ..........................................................?0.5v to v dd +0.5v current output ................................................................-25ma to +25ma power dissipation continuous ....................................................... 500mw operating temperature .............................................................. 0 to +70c note: stresses greater than those listed under max i mum rat- ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. exposure to absolute max i mum rating con di tions for ex- tended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) ac/dc electrical characteristics symbol parameter conditions min. typ. max. units i dd-standby i dd current, standby ce = lvcmos low 0.55 ma i dd-active i dd current, active ce = lvcmos high 100 p standby supply power, standby ce = lvcmos low 2 mw p active supply power, active ce = lvcmos high 360 t pd latency from input to output 2.0 ns cml receiver input z rx-dc dc input impedance 40 50 60 ohm z rx-diff-dc dc differential input impedance 80 100 120 v rx-diffp-p differential input peak-to- peak voltage 0.200 v v rx-cm-acp ac peak common mode input voltage 150 mv v th-sd signal detect threshold ce = 1 50 (2) 200 (3) mvppd s dd11_rx rx differential mode return loss 75mhz-300mhz 300mhz-600mhz 600mhz-1.2ghz 1.2ghz-2.4ghz 2.4ghz-3.0ghz 3.0 ghz-5.0ghz 18 14 10 8 3 1 db s cc11_rx rx common mode return loss 150mhz-600mhz 600mhz-1.2ghz 1.2ghz-5.0ghz 5 2 1 db s dc11_rx rx impedance balance 150mhz-600mhz 600mhz-1.2ghz 1.2ghz-2.4ghz 2.4ghz-5.0ghz 30 20 10 4 db equalization j rs residual jitter (1,2) total jitter 0.3 ulp-p j rm random jitter (1,2) 1.5 psrms notes 1. k28.7 pattern is applied differentially at point a as shown in figure 1. 2. total jitter does not include the signal source jitter. total jitter (tj) = (14.1 rj + dj) where rj is random rms jitter and dj is maximum deterministic jitter. signal source is a k28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and k28.7 (00 11111000) or equivalent for random jitter test. residual jitter is that which remains after equalizing media-induced losses of the environment of figure 1 or its equivalent. the deterministic jitter at point b must be from media-induced loss, and not from clock source modulation. jitter is measured at 0v at point c of figure 1. 3. using compliance test at 1.5gbps and 3gbps. also using oob (oob is formed by alignp primitive or d24.3) test patterns at 1.5 gbps. the align primitive (k28.5+d10.2+d27.3 = 001111 1010+0101010101+0010011100). the d24.3 = 00110011001100110011 08-0252
5 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. ac/dc electrical characteristics symbol parameter conditions min. typ. max. units cml transmitter output (100 differential) z tx-diff-dc dc differential tx impedance 80 100 120 ohm v tx-diffp-p differential peak-to-peak out- put voltage v tx-diffp-p = 2 * | v tx-d+ - v tx-d- | 250 800 mv for ros=3.2k, rem=7.3k 475 525 v tx-c common-mode voltage | v tx-d+ + v tx-d-| /2 1 1.8 v t f , t r transition time 20% to 80% (1) 150 ps t f -t r mis-match transition time 3g only; hftp, mftp 20 % v amp_bal tx amplitude imbalance 3g only; hftp, mftp 10 % t skew tx differential skew 1.5g and 3g; hftp, mftp 20 ps v cm_ac tx ac common mode voltage 3g only; mftp 50 mvpp v cmoob oob common mode delta voltage 50 mv v diffoob oob differential delta voltage 25 v tx-pre-ratio-max max tx pre-emphasis level 4 db s dd11_tx tx differential mode return loss 75mhz-300mhz 300mhz-600mhz 600mhz-2.4ghz 2.4ghz-3.0ghz 3.0 ghz-5.0ghz 14 18 6 3 1 db s cc11_tx tx common mode return loss 150mhz-300mhz 300mhz-600mhz 600mhz-1.2ghz 1.2ghz-5.0ghz 8 5 2 1 db s dc11_tx tx impedance balance 150mhz-300mhz 300mhz-600mhz 600mhz-2.4ghz 2.4ghz-5.0ghz 30 20 10 4 db lvcmos control pins v ih input high voltage 0.65 v dd v v il input low voltage 0.35 v dd i ih input high current 5 a i il input low current 100 08-0252
6 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. figure 1. test condition referenced in the electrical characteristic table d.u.t. signal source sma connector in out a sma connector b c fr4 30 in figure 2. system implementation diagram vdd xi+ xi- x_eq eq xo+ xo- x_em x_es ros rem recommended coupling capacitors are 4.7nf 2k 7 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. v d+ common mode voltage v_d+ - v_d- 0v v cm v diff v d- v diffp-p v diffp-p v d+ v cm v diff v d- 1 st t bit 2 nd + t bit(s) v diff-pre pre-emphasis = 20 . log(v diff-pre /v diff ) de nition of differential voltage and differential voltage peak-to-peak de nition of pre-emphasis 08-0252
8 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. packaging mechanical: 20-contact tqfn (zh) 1 :noitpircsed :edoc egakcap 2032 -dp :# lortnoc tnemucod a:noisiver 80/41/30 :etad zh20 20-contact, very thin quad flat no-lead, tqfn 08-0122 08-0252
9 ps9009a 04/03/09 PI3EQX3851B 3.3v, 1-port, sata2 i/m redriver? with analog output adjustment redriver is a trademark of pericom semiconductor. ordering information ordering number package code package description PI3EQX3851Bzhe zh pb-free and green 20-contact tqfn (3.5x4.5mm) PI3EQX3851Bzde zd pb-free and green 20-contact tqfn (4x4mm) notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? x suf x = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com packaging mechanical: 20-contact tqfn (zd) : 20-lead, thin fine pitch quad flat no-lead (tqfn) noitpircsed :edoc egakcap 2084 -dp :# lortnoc tnemucod -- :noisiver 80/11/90 :etad zd20 08-0456 08-0252
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